Key Specifications
State Analysis for DigRF v3-Compliant Devices
-Maximum acquisition speed: 312 Mbps
-Voltage level support: 1.8 V LVDS, 1.2 V LVDS, SLVDS
-SysClk speed support: 19.2 MHz, 26.0 MHz, 38.4 MHz
-Over air standard support: 2.5G and 3GPP (e.g. GSM, EDGE, CDMA, CDMA-2k, W-CDMA)
Monitor Device and System Operation
-Simultaneously acquires Tx/Rx bidirectional traffic
-Tracks changes across all speed modes - sleep, low power and high speed
-Displays data and control packets at the protocol level
-Triggers on protocol-specific packets, specific bits within a packet, and protocol violations
Additional Capabilities
-LEDs show DigRF v3 bus status and error conditions
-Identifies invalid sync words
-Supports up to 2048 bits for user-defined payload
-Extracts and transfers digital IQ for analysis with 89601A VSA software
Configuration Considerations
-Requires 16800 or 16900 Series logic analyzer with 68-channels or more
-High impedance probing for signal integrity E5381A
-For stimulus, add a pattern generator and N4860A DigRF v3 Digital Stimulus Probe
-Customize DigRF v3 protocol decoding with Protocol Development Kit
Description
The N4850A digital acquisition probe and N4860A digital stimulus probe operate in conjunction with 16800 and 16900 Series logic analyzers. The probes provide digital acquisition and serial stimulus capabilities required for DigRF v3 based IC evaluation and integration.
The integration of DigRF v3 logic analysis tools with the Agilent RF portfolio provides cross-domain solutions that will help you rapidly deploy your DigRF v3-based designs.
